MC68HC908LB8VDWE
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MC68HC908LB8VDWE Features:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 families
• Low-power design; fully static with stop and wait modes
• 3.3V operating voltage
• 6MHz internal bus frequency; with 24MHz external crystal
• 60,928 bytes of on-chip FLASH memory with security1 feature
• 2,048 bytes of on-chip random access memory (RAM)
• 39 general-purpose input/output (I/O) pins, including:
– 38 shared-function I/O pins
– 8-bit keyboard interrupt port
• 2-channel, 16-bit timer interface module (TIM) with selectable input capture, output compare, and PWM capability on one channel
• 6-channel, 8-bit analog-to-digital converter (ADC)
• 8-channel, 8-bit pulse width modulator (PWM)
• Sync signal processor with the following features:
– Horizontal and vertical frequency counters
– Low vertical frequency indicator (40.7Hz)
– Polarity controlled Hsync and Vsync outputs from separate sync or composite sync inputs
– Internal generated free-running Hsync, Vsync, DE, and DCLK
– CLAMP pulse output to the external pre-amp chip
• On screen display (OSD) and full screen pattern display
• Full Universal Serial Bus (USB) specification 1.1, composite hub with embedded functions, including:
– One 12MHz upstream port
– Four 12MHz/1.5MHz downstream ports
– One hub control endpoint with 8-byte transmit buffer and 8-byte receive buffer
– One hub interrupt endpoint with 1-byte transmit buffer
– One device control endpoint with 8-byte transmit buffer and 8-byte receive buffer
– Two device interrupt endpoints with shared 8-byte transmit buffer
• DDC12AB1 module with the following:
– DDC1 hardware
– Multi-master IIC2 hardware for DDC2AB; with dual address
• Additional multi-master IIC module
• In-system programming capability using USB or DDC12AB
communication, or standard serial link on PTA0 pin
• System protection features:
– Optional computer operating properly (COP) reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• Master reset pin (with internal pull-up) and power-on reset
• IRQ interrupt pin with internal pull-up and schmitt-trigger input
• 64-pin quad flat pack (QFP) package
详细介绍请参考:
MOTOROLA MC68HC908LB8VDWE技术手册:MC68HC908LB8VDWE.PDF
提供MOTOROLA MC68HC908LB8VDWE单片机解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 families
• Low-power design; fully static with stop and wait modes
• 3.3V operating voltage
• 6MHz internal bus frequency; with 24MHz external crystal
• 60,928 bytes of on-chip FLASH memory with security1 feature
• 2,048 bytes of on-chip random access memory (RAM)
• 39 general-purpose input/output (I/O) pins, including:
– 38 shared-function I/O pins
– 8-bit keyboard interrupt port
• 2-channel, 16-bit timer interface module (TIM) with selectable input capture, output compare, and PWM capability on one channel
• 6-channel, 8-bit analog-to-digital converter (ADC)
• 8-channel, 8-bit pulse width modulator (PWM)
• Sync signal processor with the following features:
– Horizontal and vertical frequency counters
– Low vertical frequency indicator (40.7Hz)
– Polarity controlled Hsync and Vsync outputs from separate sync or composite sync inputs
– Internal generated free-running Hsync, Vsync, DE, and DCLK
– CLAMP pulse output to the external pre-amp chip
• On screen display (OSD) and full screen pattern display
• Full Universal Serial Bus (USB) specification 1.1, composite hub with embedded functions, including:
– One 12MHz upstream port
– Four 12MHz/1.5MHz downstream ports
– One hub control endpoint with 8-byte transmit buffer and 8-byte receive buffer
– One hub interrupt endpoint with 1-byte transmit buffer
– One device control endpoint with 8-byte transmit buffer and 8-byte receive buffer
– Two device interrupt endpoints with shared 8-byte transmit buffer
• DDC12AB1 module with the following:
– DDC1 hardware
– Multi-master IIC2 hardware for DDC2AB; with dual address
• Additional multi-master IIC module
• In-system programming capability using USB or DDC12AB
communication, or standard serial link on PTA0 pin
• System protection features:
– Optional computer operating properly (COP) reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• Master reset pin (with internal pull-up) and power-on reset
• IRQ interrupt pin with internal pull-up and schmitt-trigger input
• 64-pin quad flat pack (QFP) package
详细介绍请参考:
MOTOROLA MC68HC908LB8VDWE技术手册:MC68HC908LB8VDWE.PDF
提供MOTOROLA MC68HC908LB8VDWE单片机解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655