ST72F621L4M
浏览次数:0
ST72F621L4M Features:
· Memories
– 8K or 16K Program memory
(ROM, FASTROM or Dual voltage FLASH)
with read-write protection
– In-Application and In-Circuit Programming for
FLASH versions
– 384 to 768 bytes RAM (128-byte stack)
· Clock, Reset and Supply Management
– Enhanced Reset System (Power On Reset)
– Low Voltage Detector (LVD)
– Clock-out capability
– 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal
frequencies)
– 3 Power saving modes
· USB (Universal Serial Bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs specification (v 1.1) and
USB HID specification (v 1.0):
– Integrated 3.3V voltage regulator and transceivers
– Suspend and Resume operations
– 3 Endpoints
· Up to 31 I/O Ports
– Up to 31 multifunctional bidirectional I/O lines
– Up to 12 External interrupts (3 vectors)
– 13 alternate function lines
– 8 high sink outputs
(8 mA@0.4 V/20 mA@1.3 V)
– 2 true open drain pins (N buffer 8 mA@0.4 V)
· 3 Timers
– Configurable watchdog timer (8 to 500 ms
timeout)
– 8-bit Auto Reload Timer (ART) with 2 Input
Captures, 2 PWM outputs and External Clock
– 8-bit Time Base Unit (TBU) for generating periodic
interrupts cascadable with ART
详细介绍请参考:
ST ST72F621L4M技术手册:ST72F621L4M.PDF
提供ST ST72F621L4M 芯片解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655
· Memories
– 8K or 16K Program memory
(ROM, FASTROM or Dual voltage FLASH)
with read-write protection
– In-Application and In-Circuit Programming for
FLASH versions
– 384 to 768 bytes RAM (128-byte stack)
· Clock, Reset and Supply Management
– Enhanced Reset System (Power On Reset)
– Low Voltage Detector (LVD)
– Clock-out capability
– 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal
frequencies)
– 3 Power saving modes
· USB (Universal Serial Bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs specification (v 1.1) and
USB HID specification (v 1.0):
– Integrated 3.3V voltage regulator and transceivers
– Suspend and Resume operations
– 3 Endpoints
· Up to 31 I/O Ports
– Up to 31 multifunctional bidirectional I/O lines
– Up to 12 External interrupts (3 vectors)
– 13 alternate function lines
– 8 high sink outputs
(8 mA@0.4 V/20 mA@1.3 V)
– 2 true open drain pins (N buffer 8 mA@0.4 V)
· 3 Timers
– Configurable watchdog timer (8 to 500 ms
timeout)
– 8-bit Auto Reload Timer (ART) with 2 Input
Captures, 2 PWM outputs and External Clock
– 8-bit Time Base Unit (TBU) for generating periodic
interrupts cascadable with ART
详细介绍请参考:
ST ST72F621L4M技术手册:ST72F621L4M.PDF
提供ST ST72F621L4M 芯片解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655