ST72F63BE2M
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ST72F63BE2M Features:
· Memories
– 4, 8, 16 or 32 Kbytes program memory: high
density Flash (HDFlash), FastROM or ROM
with Read-Out and Write protection
– In-application programming (IAP) and in-circuit
programming (ICP)
– 384, 512 or 1024 bytes RAM memory (128-
byte stack)
· Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
– RAM Retention mode
– Optional low voltage detector (LVD)
· USB (universal serial bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID specifications
(version 1.0)
– Integrated 3.3 V voltage regulator and transceivers
– Supports USB DFU class specification
– Suspend and Resume operations
– 3 endpoints with programmable Input/Output
configuration
· Up to 27 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os (25 mA
at 1.5 V)
– Up to 8 lines individually programmable as interrupt
inputs
· 1 analog peripheral
– 8-bit A/D converter with 8 or 12 channels
· 2 timers
– Programmable watchdog
– 16-bit timer with 2 Input Captures, 2 Output
Compares, PWM output and clock input
· 2 communication Interfaces
– Asynchronous serial communications Interface
– I²C multimaster Interface up to 400 kHz
详细介绍请参考:
ST ST72F63BE2M技术手册:ST72F63BE2M.PDF
提供ST ST72F63BE2M 芯片解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655
· Memories
– 4, 8, 16 or 32 Kbytes program memory: high
density Flash (HDFlash), FastROM or ROM
with Read-Out and Write protection
– In-application programming (IAP) and in-circuit
programming (ICP)
– 384, 512 or 1024 bytes RAM memory (128-
byte stack)
· Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
– RAM Retention mode
– Optional low voltage detector (LVD)
· USB (universal serial bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID specifications
(version 1.0)
– Integrated 3.3 V voltage regulator and transceivers
– Supports USB DFU class specification
– Suspend and Resume operations
– 3 endpoints with programmable Input/Output
configuration
· Up to 27 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os (25 mA
at 1.5 V)
– Up to 8 lines individually programmable as interrupt
inputs
· 1 analog peripheral
– 8-bit A/D converter with 8 or 12 channels
· 2 timers
– Programmable watchdog
– 16-bit timer with 2 Input Captures, 2 Output
Compares, PWM output and clock input
· 2 communication Interfaces
– Asynchronous serial communications Interface
– I²C multimaster Interface up to 400 kHz
详细介绍请参考:
ST ST72F63BE2M技术手册:ST72F63BE2M.PDF
提供ST ST72F63BE2M 芯片解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655