C8051F220芯片解密
浏览次数:0
C8051F220 25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
C8051F220 Analog Peripherals
8-Bit ADC
-±1/2 LSB INL; no missing codes
-Programmable throughput up to 100 ksps
-32 external inputs (each port I/O can be configured as an ADC input on-the-fly)
-Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-Data-dependent windowed interrupt generator
-VREF from external pin or VDD
Two comparators
-Programmable hysteresis
-Configurable to generate interrupts or reset
VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
-On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation
-Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers
-Superior performance to emulation systems using ICE-chips, target pods, and sockets
-Fully compliant with IEEE 1149.1 specification
High-Speed 8051 μC Core
-Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz system clock
-Expanded interrupt handler; up to 21 interrupt sources
Memory
-256 bytes data RAM
-8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved)
Digital Peripherals
-32 port I/O; all are 5 V tolerant
-Hardware SPI™ and UART serial ports available concurrently
-3 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
Clock Sources
-Internal programmable oscillator: 2–16 MHz
-External oscillator: Crystal, RC, C, or Clock
-Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-Typical operating current: 9 mA at 25 MHz
-Typical stop mode current: <0.1 uA
48-Pin TQFP
-Temperature Range: –40 to +85 °C
详细介绍请参考:
C8051F220技术手册:C8051F220.PDF
提供Silicon C8051F220单片机解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655
C8051F220 Analog Peripherals
8-Bit ADC
-±1/2 LSB INL; no missing codes
-Programmable throughput up to 100 ksps
-32 external inputs (each port I/O can be configured as an ADC input on-the-fly)
-Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-Data-dependent windowed interrupt generator
-VREF from external pin or VDD
Two comparators
-Programmable hysteresis
-Configurable to generate interrupts or reset
VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
-On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation
-Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers
-Superior performance to emulation systems using ICE-chips, target pods, and sockets
-Fully compliant with IEEE 1149.1 specification
High-Speed 8051 μC Core
-Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz system clock
-Expanded interrupt handler; up to 21 interrupt sources
Memory
-256 bytes data RAM
-8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved)
Digital Peripherals
-32 port I/O; all are 5 V tolerant
-Hardware SPI™ and UART serial ports available concurrently
-3 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
Clock Sources
-Internal programmable oscillator: 2–16 MHz
-External oscillator: Crystal, RC, C, or Clock
-Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-Typical operating current: 9 mA at 25 MHz
-Typical stop mode current: <0.1 uA
48-Pin TQFP
-Temperature Range: –40 to +85 °C
详细介绍请参考:
C8051F220技术手册:C8051F220.PDF
提供Silicon C8051F220单片机解密服务,仅限学习、研究等合法用途。
联系方式:010-62245566 13810019655